The invention relates to an improvement in the chip addressing and selecting controls for a processor memory with cache in a data processing system.
The most commonly used cache directory found in current commercial computer systems is a hardware matrix in which the matrix rows contain respective cache congruence classes, in which each cache class has a plurality of associative entries, and each entry is capable of containing a main storage address representation for a line of words in an associated cache data storage array. The directory entries may be conceptually considered to be arranged in the respective columns (i.e. sets) of the matrix. The entries in any row found in the different columns are set-associative,
In the prior art, U.S. Pat. No. 3,705,388 interrupts main storage while it is transferring a line of data to a cache to permit a processor (CPU) to access a different line of data in the cache. U.S. Pat. Nos. 3,670,307 and 3,670,309 enable concurrent processor and line fetch accesses by accessing different basic storage modules (BSMs) in the cache; that is, the processor can access the busses of one BSM of a cache concurrently with a line fetch from main storage accessing the different busses of another BSM of the cache, which must be constructed with plural BSMs. U.S. Pat. No. 3,588,829 delays a processor request to the cache from the first word of a line transfer until after the last word of the line fetch is completed from main storage to the cache. U.S. Pat. No. 3,806,888 provides fast readout means in the main memory so that on each line of data can be transferred through a buffer to a cache in the time normally required to transfer word from main memory.
The unit of data transferred between main memory and cache of a general purpose computer is called a "cache line". Each cache line consists of one or more elements; the number of elements (E) in a cache line is known as the line length L. The width of the data path between main memory and cache is called W. This implies that the transfer of a cache line takes L/W transfers on the data path.
An undesirable delay occurs when:
a) the line length L is a multiple of the data path width W PA1 b) the data path width W is a multiple of the element length E PA1 c) the cache line load is caused by the CPU trying to access a string of elements that is currently not in the cache and that is not longer than L.
The solution to this problem according to the above mentioned prior art is to load the cache line starting with the W elements, aligned on a W-element boundary, containing the first of the elements that caused the cache miss. The boundary alignment restriction is introduced to simplify the hardware design. The problem is that the CPU might need a string of elements contained in W1 or W2 or W3 or W5 or W6 or W7. In this case the CPU has to wait for the second, third or fourth data transfer to be completed before it can proceed.
Therefore it is an object of this invention to provide a method of the chip addressing and selecting controls in the main memory of a data processor system including a cache by avoiding the unwanted wait transfers.
Another object of the invention is to provide a hardware solution for the method of the invention, using very moderate additional hardware means.